The present invention relates generally to integrated circuit memory devices and, more particularly, to identifying weak pull-up PFETs contained within a Static Random Access Memory (SRAM) cell.
A typical static random access memory (SRAM) cell includes an array of individual SRAM cells. Each SRAM cell is capable of storing a binary voltage value therein, which voltage value represents a logical data bit (e.g., xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d). One existing configuration for an SRAM cell includes a pair of cross-coupled devices such as inverters. With CMOS (complementary metal oxide semiconductor) technology, the inverters further include a pull-up PFET (p-channel) transistor connected to a complementary pull-down NFET (n-channel) transistor. The inverters, connected in a cross-coupled configuration, act as a latch which stores the data bit therein so long as power is supplied to the memory array. In a conventional six-transistor cell, a pair of access transistors or pass gates (when activated by a word line) selectively couple the inverters to a pair of complementary bit lines.
As memory devices continue to shrink in size over time, so do the individual cells and hence the individual devices within the cell. One problem associated with SRAM device miniaturization occurs as a result of an unstable threshold voltage (VT) of the PFETs. In a typical six transistor SRAM cell layout, the PFETs are minimally sized in order to allow for maximum array density. A relatively small PFET, in turn, may exhibit an excessively high shift in VT after module stress. As the VT of the PFET approaches the supply voltage (VDD), the six-transistor cell becomes a dynamic four-transistor cell. Moreover, in a cell with a weak pull-up PFET, a xe2x80x9chighxe2x80x9d cell node will eventually drift to ground over time, since the NFET to ground current (when the NFET is xe2x80x9coffxe2x80x9d) is the dominating leakage current within the cell. In such a case, a cell which has a xe2x80x9c1xe2x80x9d bit stored therein may, over time, flip to a xe2x80x9c0xe2x80x9d bit before a read operation is later performed. The reverse may also be true if both PFETs are weak or if the PFET associated with the complementary bit line is weak.
Unfortunately, during conventional SRAM testing, a cell with a weak PFET(s) may appear healthy. In addition, the SRAM bit line circuitry can accidentally refresh the cell nodes during a read operation, thereby helping to hide the problem. As a selected word line is activated, all cells connected thereto are exposed to the bit line bias, which was set to VDD during a restore operation. If both PFETs within the cell are equally weak, and if the high cell node had drifted down near ground, both cell nodes will be pulled up to about the same level through the passgates. Eventually, if the inactive standby time is long enough, both cell nodes will drift back down toward ground and at about the same voltage level. In such cases where the voltage difference between the left cell node and the right cell node is about zero, the cell is considered to have been disturbed to the xe2x80x9cXxe2x80x9d state.
During a subsequent read operation, an SRAM cell in the xe2x80x9cXxe2x80x9d state may or may not fail the test. A cell in the xe2x80x9cXxe2x80x9d state which passes the test is considered a problematic escapee. If only one of the PFETs is weak, and the cell is at the state where the weak PFET should be turned off, then the defect is virtually undetectable. Unlike a dynamic random access memory (DRAM) cell where the data loss is mainly from the xe2x80x9c1xe2x80x9d state to the xe2x80x9c0xe2x80x9d state, an SRAM cell that has lost data may in certain instances be read as a healthy cell. Present screening methods for identifying weak pull-up PFETs, therefore, are a xe2x80x9chit or missxe2x80x9d venture. In practice, some screening methods involve shortening the test cycle time and lowering the power supply VDD, thereby trying to make the weak cells fail the write operation. Other existing methods modify the write cycle to allow a xe2x80x9cweak writexe2x80x9d operation to flip the weak cells. However, these existing weak write operations are too strong, thereby allowing good cells to be screened out by mistake.
The above discussed and other drawbacks and deficiencies of the prior art are overcome or alleviated by a method for determining the memory cell stability of individual memory cells included within a memory array. In an exemplary embodiment, the method includes presetting each memory cell to a first logic state and then applying a gradually increasing, controlled leakage current to a node within each memory cell. The voltage of each of the nodes within each corresponding memory cell is then monitored. Then, for each memory cell within the memory array, the level of leakage current which causes the memory cell to be changed from the first logic state to a second logic state is determined. The level of leakage current which causes the memory cell to be changed from the first logic state to the second logic state corresponds to the threshold voltage of a pull-up PFET within the memory cell.